Senior Cache and Memory Design Engineer-Barcelona

As a Senior Cache and Memory Design Engineer, you will be a key player in designing and developing memory subsystem solutions for our semiconductor portfolio. Your role will involve collaborating with the Cache and Memory Design Team and other highly skilled engineers to create efficient and high-performance memory subsystems that are critical for modern designs. Key Responsibilities: - Define address map, CHI and CXL protocols, cache, and bank memories - Utilize RTL design using Verilog or VHDL for efficient implementation - Proficient in scripting languages such as Python, Perl, Bash, and TCL - Experience with Timing and Timings Constraints for optimizing performance - Familiarity with revision control methodology and tools like git and svn - Conduct basic block level testing to ensure functionality - Knowledge of LDDR5-6 for memory subsystem design Qualifications Required: - Master's or PhD degree in a relevant field - English proficiency at C1 level - Minimum of 8 years of industrial experience in microprocessor architecture - Understanding of coherency principles in memory subsystem design Join our team and be part of a dynamic environment where your expertise in cache and memory design will contribute to cutting-edge semiconductor solutions. As a Senior Cache and Memory Design Engineer, you will be a key player in designing and developing memory subsystem solutions for our semiconductor portfolio. Your role will involve collaborating with the Cache and Memory Design Team and other highly skilled engineers to create efficient and high-performance memory subsystems that are critical for modern designs. Key Responsibilities: - Define address map, CHI and CXL protocols, cache, and bank memories - Utilize RTL design using Verilog or VHDL for efficient implementation - Proficient in scripting languages such as Python, Perl, Bash, and TCL - Experience with Timing and Timings Constraints for optimizing performance - Familiarity with revision control methodology and tools like git and svn - Conduct basic block level testing to ensure functionality - Knowledge of LDDR5-6 for memory subsystem design Qualifications Required: - Master's or PhD degree in a relevant field - English proficiency at C1 level - Minimum of 8 years of industrial experience in microprocessor architecture - Understanding of coherency principles in memory subsystem design Join our team and be part of a dynamic environment where your expertise in cache and memory design will contribute to cutting-edge semiconductor solutions.