Senior Cache and Memory Design Engineer-Barcelona

As a Senior Cache and Memory Design Engineer, you will be responsible for designing and developing memory subsystem solutions for the semiconductor portfolio. Working within the Cache and Memory Design Team, you will collaborate with highly skilled engineers from other teams to create efficient and high-performance memory subsystems critical for modern designs. Key Responsibilities: - Define address map, CHI and CXL protocols, cache, and bank memories - Utilize proficiency in RTL design using Verilog or VHDL - Apply knowledge of scripting languages such as Python, Perl, Bash, and TCL - Experience with Timing and Timings Constraints - Familiarity with revision control methodology and tools like git and svn - Conduct basic block level testing Qualifications Required: - Master's or PhD degree in a relevant field - English proficiency at C1 level - Minimum of 8 years of industrial experience - Knowledge of coherency - Familiarity with LDDR5-6 technology Join our team if you are passionate about microprocessor architecture and eager to contribute to the development of cutting-edge memory subsystem solutions.,