Senior ASIC RTL Engineer

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Senior ASIC RTL Engineer

Key Responsibilities

• RTL for IPs, subsystems, and SoC integration

• RTL quality checks

• static checks

• IP, cluster, and SoC level

• PD, Verification, DFT, and SW teams

• design documentation

• Debug complex design issues across multiple blocks and interfaces

Mandatory Skills

1. RTL Design, Coding & Integration (Verilog / SystemVerilog)

2. RTL Quality Checks Lint & CDC (Spyglass)

3. SoC / IP / Subsystem Design & Integration

4. AMBA Bus Protocols (AXI, AHB, APB, ATB)

5. Interface Protocols PCIe / DDR / Ethernet / I2C / UART / SPI

Additional Skills (Good to Have)

• synthesis and low-power techniques

• timing concepts

• Spyglass, Synopsys DC, Verdi, Xcellium

• Make, Perl, Shell, Python

• processor architecture and/or ARM debug architecture

If you have strong expertise in ASIC RTL and SoC/IP design and enjoy working on complex silicon subsystems and protocols, wed be happy to have you apply and be part of our growing engineering team.