RTL Verification Engineer - System Verilog

As a skilled Hardware Verification Engineer, you will be an integral part of our team, contributing to the development of cutting-edge hardware solutions. Your primary responsibilities will include developing and maintaining System Verilog /UVM test-benches at various levels, defining and driving test plans, engaging in verification environment architecture, collaborating with design teams, generating comprehensive documentation, and performing hardware testing using a variety of test equipment. You should possess strong experience in SystemVerilog and UVM-based verification, proficiency in verifying standard protocols such as Ethernet, PCIe, SPI, I2C, and USB, hands-on experience with hardware test equipment, familiarity with Xilinx FPGA verification and toolchains, strong debugging skills, and proficiency in scripting languages like Perl, Python, or TCL. Additionally, you should have excellent analytical, problem-solving, and communication skills, with the ability to work effectively in a collaborative and fast-paced development environment. Experience with code and functional coverage collection and analysis tools, constraint random verification, assertion-based verification, simulation acceleration, emulation, formal verification tools, SoC architecture, DMA, memory controllers, bus interfaces, version control systems, CI/CD verification automation, Agile/Scrum environments, cloud-based verification environments, coverage-driven verification, and verification management tools will be considered as additional relevant skills. By joining us, you will have the opportunity to work on next-generation products in a technically driven team, with growth opportunities in both frontend and backend design flows. You will also benefit from a supportive work environment with access to advanced labs and equipment.,