Job
Description
You are a seasoned professional in RTL Design and Signoff , bringing a wealth of experience and expertise to the table. You have a keen understanding of the complexities of RTL Quality Signoff and are adept at proposing resource requirements to meet project goals. Your leadership skills are top-notch, allowing you to guide a team of engineers through various pre-silicon static verification activities on IPs/Subsystems . You have a strong grasp of design and architecture , enabling you to develop precise timing constraints for synthesis and timing . Your ability to ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products ensures that you stay ahead of the curve. You collaborate effectively with peers to enhance methodology and execution efficiency. Your excellent communication skills facilitate smooth interactions with Synopsys customers, BU AEs, Sales teams, and other stakeholders. With a minimum of 8+ years of experience , you are well-versed in debugging, diagnosing violations, and setting up flows and methodologies for quick RTL Signoff tool deployment . Your technical expertise in LINT, CDC, RDC, and timing constraints development is unparalleled. You are a strategic thinker with a strong understanding of design concepts, ASIC flows, and stakeholder management . What You'll Be Doing: Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Lead a team of engineers to perform various pre-silicon static verification activities on IPs/Subsystems. Develop timing constraints for synthesis and timing while understanding the design/architecture. Collaborate with peers to improve methodology and enhance execution efficiency. Ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers. Work with other Synopsys teams, including BU AEs and Sales, to develop, broaden, and deploy Tool and IP solutions. Set up flows and methodologies to enable quick setup for RTL Quality checks, Synthesis, and Formality. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Ensure high-quality RTL Signoff and design, contributing to the success of Synopsys projects. Lead the team in delivering precise and efficient pre-silicon static verification activities. Enhance the overall execution efficiency of RTL Design and Signoff processes. Enable customers to achieve their goals through the deployment of Synopsys Products and methodologies. Develop and implement innovative solutions for RTL Quality Signoff in the semiconductor industry. Strengthen Synopsys reputation as a leader in chip design, verification, and IP integration. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 8+ years experience in RTL Design and Verification. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise in setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead a team to perform RTL Signoff on complex SoC/IP/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.
