5 Rdma Jobs

Your Opportunity As an HPC Architect , you will get the opportunity to architect high-performance computing solutions from scratch and design/ optimize all aspects (Compute , Memory, Network ing , Storage) for better cost of Ownership. Roles and Responsibility As an architect, you will be responsible fordesigning HPC infrastructure solutions, including compute, networking, storage, and workload management components. You will work closely with cross-functional teams, including Hardware, Software, product management, and business stakeholders, to understandcomputeworkload and translate theminto Platformarchitecture and designs that meet business needs. You will create and maintain detailed system architecture diagrams and specifications. You will evaluate and select appropriate hardware and software components for HPC environments You will Install, configure, and maintain HPC systems, including hardware, software, and networking components You will develop and implement automation scripts for system management and deployment. You will be a subject Matter expert to unblock dependent teams in the HPC domain. You will be expected to develop system benchmarks, profile systems to understand bottlenecks, optimize workflows and processes to improve cost of ownership. Identify and mitigate technical risks and issues throughout the HPC development life cycle. Ensure that ComputeCluster is resilient, reliable, and maintainable. You will be expected to stay abreast of the latest HPC technologies, including Hardware, Software and Networking Solutions Your primary focus will be to understand thecomputeworkload and design HPC cluster with right combination of Nodes, CPU/GPU, Memory, Interconnects and storageto have optimum performance at minimum cost of Ownership. Our Ideal Candidate Someone who has the drive and passion to learn quickly , has the ability to multi- task and switch contexts based on business needs . Qualifications In-depth experience with Linux System administration and Hardware/Software Configuration. Strong knowledge of HPC technologies including cluster computing, high speed interconnects (InfiniBand, RoCE), parallel filesystems (Lustre, GPFS, BeeGFSetc) Experience in creating, maintaining Operating System images with different installation and boot schemes Extremely good with automation tools like Ansible, Chef, Salt-Stack and Scripting languages (Python and Bash) Experience in Creating,maintaining Storage Solutions with different RAID configuration. Ability to design storage solution for different IOPS, Access patterns (Random vs Sequential RW) and tune storage and filesystemsfor better performance. Good of knowledgeNetworking concepts including IP addressing, routing, protocols and Switch configuration for RDMA, VLAN configuration, network bonding etc. Good Knowledge Virtualization, Hardware and Software Hypervisors Good knowledge of containerization technologies like docker, singularity. Experience in Software Defined Networking and Storage. Experience in setting-up remote management protocols like IPMI, Redfish etc. Experience in setting-up and using monitoring systems like Prometheus, Grafana. Experience System profiling and custom tuningfor targetworkloadfor higher performance and low cost of ownership Very good written and verbal communication skills. Very goodinTechnical documentation meant to serve as manuals for non-experts in the field. Additional Qualifications: Experience in HPC Cluster management and Work-load orchestration software (e.g.SLURM, Torque, LSF) Experience in Setting-up Deep-learning training/inference solutions. Experience in Private cloud infrastructure like Kubernetes, OpenStack,CloudStack etc. Experience in DistributedHigh Performance Computing and Parallel programming frameworks Good knowledge of Low-latency and high-throughput data transfer technologies(RDMA on RoCE, InfiniBand) Education : Bachelor's Degree or higher in Computer science or related Disciplines.

Skillset: DV | System Verilog | UVM | Protocol Expertise Must-Have Skills: Strong expertise in System Verilog (SV) and UVM Proven experience in Test Bench Development Deep protocol knowledge in at least one of the following: PCIe / UCIe / CXL / NVM AXI / ACE / CHI Ethernet / RoCE / RDMA DDR / LPDDR / HBM Key Responsibilities : Lead and drive verification for block, subsystem, or SoC level designs Strong experience in IP/subsystem/SoC verification using SV/UVM Verification experience with ARM or RISC-V CPU based subsystems Work with C/Assembly for low-level testing Perform Power Aware Simulations using UPF Location : Bangalore | Hyderabad | Cochin | Pune

Bachelor's degree in Computer Science with 10+ years of experience with HPC environments Experience in HPC architecture and design, with a proven track record of delivering complex HPC solutions. Experience in designing and implementing HPC solutions on public cloud, private cloud, and on-premises infrastructure. Knowledge of HPC technologies, including M PI, OpenMP, Infiniband, GPFS, Lustre , and other file systems, cluster management tools such as Slurm , Torque, or LSF, and scheduling software such as PBSPro. Excellent communication skills, including the ability to communicate technical concepts to both technical and non-technical audiences. Experience with virtualization and containerization technologies such as Docker, Kubernetes, and Singularity. Strong understanding of networking technologies and protocols, including TCP/IP, Infiniband, and RDMA. Familiarity with one or more programming languages such as C, C++, Fortran, Python, or Java. Experience working in a multi-vendor, multi-cloud environment. Strong problem-solving skills and the ability to work under pressure in a fast-paced environment. Suitable candidates may forward their updated profiles in strict confidence to hr33@hectorandstreak.com or call on 9699224920

ASIC Design Verification Engineer || UVM/System Verilog || Test benches || Exp 4 to 7 years Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle. Your Impact You will contribute to developing Ciscos revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include: Architect block, cluster and top-level DV environment infrastructure. Develop DV infrastructure from scratch for block and cluster level environments. Maintain and enhance existing DV environments. Develop test plans and tests for qualifying design at block, and cluster level environments with mix of constraint random and directed stimulus. Ensure complete verification coverage through implementation and review of code and functional coverage. Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist. Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance. Support testing of design in emulation. Minimum Qualifications Bachelors Degree in EE, CE, or other related fi eld. 5+ years of related ASIC design verification experience. Proficient in ASIC verification using UVM/System Verilog. Proficient in verifying complex blocks and/or clusters for ASIC. Experience building test benches from scratch, hands on experience with SystemVerilog constraints, structures and classes. Scripting experience with Perl and/or Python. Preferred Qualifications Experience with Forwarding logic/Parsers/P4. Experience with Veloce/Palladium/Zebu/HAPS. Formal verification (iev/vc formal) knowledge. Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

Principal IP/RTL Design Engineer for Ethernet Switch Bangalore / Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"