Principal Engineer, Physical Design Timing

About The Role

In this role, you will be responsible for Timing methodology definition and closure of designs using industry standard tools for chiplet designs for custom and domain specific products. The chiplets will be leveraged to enable modular design and support multiple products. As part of this team, the candidate will work with leading edge technologies and solutions across multiple domains including SoC multi-die implementations (2.5 and 3D), power delivery, leading edge memory technologies, innovate thermal solutions, on die clocking, and fabrics. The team will also look at options to enhance product power/performance/area/cost thru improved tools and methodologies. The successful candidate would be expected to:Responsibilities1. Drive PV convergence/signoff, including static timing, ERC checks, ECO flows and power analysis2. Defining clock frequencies, PV guard-banding, signoff PV corners, ERC checks, Clock/Reset domain crossing design constraints3. Develop and recommend design methodologies to enable more efficient and faster design convergence4. Scripting in an interpreted language (TCL, py)5. Ability to work independently and at various levels of abstraction6. Strong analytical ability and problem solving skills7. Ability to work effectively with both internal and external teams/customers is expected.8. Strong written and verbal communication skills9. Ability to mentor other engineers and technically guide them.

Qualifications

Minimum Qualifications:1. Bachelor/Master degree in CS, CE or EE or equivalent experience2. 10+ years of Physical design experience with a strong understanding of digital circuits and proficiency in static timing analysis (STA) tools like PrimeTime or Innovus.3. Experience with signoff corner selection, PV guard-banding, PV convergence, including static timing and power analysis4. Strong experience in SoC and ASIC design flows on taped out designs5. Expertise in timing closure at block/chip level and ECO flows6. Experience with scripting in an interpreted languagePreferred Qualifications:1. Experience with full chip integration, die-to-die and package integration level timing signoff

2. Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools

3. Strong experience in CPU and GPU design flows on taped out designs4. Design tools and methods development

5. Capable of working in a high performing team to deliver the results required from the organization.

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