Principal Design Verification Engineer

Your Team, Your Impact

Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M product families. The SoC family of multi-core CPU processors and Custom SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers specifications, whether they re a major telecom organization or automotive company, etc.

What You Can Expect

• Lead the design verification of complex CPU sub-systems and the full chip.
• Hands-on work on a test bench architecture, test bench development, test plan, and coverage plan is needed.
• Mentor and guide a team of design verification engineers.
• Own the subsystem verification flows, methodologies, and verification of IP/subsystem conclude with the required verification criteria.

What Were Looking For

• Bachelor s degree in computer science, electrical engineering, or related fields and 12-15 years of related professional experience.
• Master s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 10+ years of experience.
• Experience with processors and SOC architectures, such as interrupt controllers & Arm CPU sub-systems, is a must.
• Experience with SoC verification is a must.
• Experience with digital design verification at the SoC level.
• Proven track record in ASIC verification, from environment development to test development
• Candidates should have hands-on verification experience and proficiency using SystemVerilog and UVM.
• Should have experience in the constrained-random stimulus and use of functional coverage.
• Exposure to the C language is preferred.
• Strong debug skills and experience with debug tools such as Verdi and Incisive.
• Good knowledge of AMBA protocols AXI, AHB, APB
• Creating a test bench, test plan, and coverage plan from scratch by hand on at least one complex project.
• Knowledge of the GIT version control system.