physical integration and verification Engineer

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success.

THE PERSON:

A successful candidate will work on full chip SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Drive Full chip physical integration and verification (DRC/LVS, ERC, DFM checks)
• Work with fab and fab contacts for all the tapeout activities leading to final tapeout.
• Work closely with physical design implementation and signoff team to achieve faster TAT
• Work closely with CAD team to come up with new flows and methodologies in the physical verification domain

PREFERRED SKILLSET:

• Experience : More that 12 years of relevant experience.
• Driven multiple tapeouts across different technology nodes
• Sound knowledge of full chip physical integration and verification flows
• Hands on experience on industry standard tools such as Calibre and ICV
• Sound understanding for DRC/LVS decks. Should be able to make updates as required.
• Good in scripting languages such as Tcl and Perl
• Self driven, positive attitude and team worker

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering