Physical Design Lead

We are seeking a highly experienced and motivated PhysicalDesignLead and PhysicalDesignManager to lead our physicaldesignteam. The successful candidate will oversee the full physicaldesigncycle, from synthesis to GDSII, for complex SoCs. This position requires deep expertise in physicaldesignmethodologies, hands-on experience in advanced process nodes (5nm, 7nm, or 10nm), and a strong leadership background to guide the team toward successful tapeouts. Key Responsibilities: Achieve timing closure across multi-mode, multi-corner scenarios. Manage and execute tapeout cycles for multiple chips. Oversee and drive the complete PhysicalDesign(PD) life-cycle, including floorplanning, placement, and routing. Handle the ECO (Engineering Change Order) life-cycle effectively. Perform Clock-Tree Synthesis (CTS) and ensure optimal clock distribution. Implement power-aware PD flows, including AutomatedDesignMethodologies (ADM) and Place & Route (P&R). Conduct PhysicalDesignStatic Timing Analysis (PD-STA) and develop timing constraints. Qualifications: Qualification: BE/B.Tech or ME/M.Tech in Electronics & Communication, Electrical & Electronics, VLSI, or a relevant field 6+ years of hands-on experience in Physical Design (PD) engineering. Proven experience in managing tapeout cycles for multiple chips. Experience with advanced process nodes (5nm, 7nm, or 10nm) is highly desirable. Strong expertise in the complete PD life-cycle, from floorplanning to final sign-off. Proficiency in ECO life-cycle management. In-depth knowledge of Clock-Tree Synthesis (CTS) and power-aware PD flows. Experience with PD-STA, timing constraint development, and achieving timing closure in multi-mode, multi-corner environments. Familiarity with industry-standard tools and methodologies used in PhysicalDesign.