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Physical Design Engineer

Physical Design Engineer

Tuitions Tree

10 years

0 Lacs

Hyderabad Telangana India

Posted:2 days ago| Platform:

Apply

Skills Required

design technology signal cadence timing verification checks power planning constraints

Work Mode

On-site

Job Type

Full Time

Job Description

Position:

Physical Design Engineer

Experience Level

1 Engineer: 10+ Years
1 Engineer: 6–8 Years
1 Engineer: 3–5 Years

Location:

Hyderabad / Bangalore (On-site)

Technology Node:

28nm – Global Foundries

Job Type:

Full-time

Notice Period:

Immediate to 30 Days preferred

Key Requirements

Strong hands-on experience in Analog and Mixed Signal SoC Implementation.
Experience with Mixed Signal and Digital Hierarchical SoC Design.
Solid understanding of Place & Route (PnR) and Signoff flows.
Expertise in Cadence EDA Tools including:

Innovus
Tempus
Genus

Working knowledge in 28nm technology node – preferably Global Foundries (GF-28nm).
Proficient in Timing Closure, Physical Verification (PV), and Signoff Checks.

Good To Have

Experience with low-power SoC implementation.
Familiarity with hierarchical floor planning and design constraints.

Skills: eda tools,physical verification (pv),pnr,innovus,signoff flows,cadence eda tools,digital hierarchical,analog and mixed signal soc implementation,low-power soc implementation,physical design,soc,genus,tempus,analog,signoff,hierarchical floor planning,place & route (pnr),design constraints,signoff checks,cadence,mixed signal soc implementation,mixed signal and digital hierarchical soc design,timing closure

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Physical Design Engineer