Physical Design Engineer

Role & responsibilities

• Perform end-to-end physical design flow: floorplanning, placement, clock-tree synthesis (CTS), routing, optimization, timing closure, and signoff
  
• Work on block-level / chip-level designs, integrating multiple IP blocks
  
• Drive optimizations for Area, Power, Performance (PPA trade-offs)
  
• Interface with RTL/logic design, system architecture, and verification teams to meet overall design goals
  
• Perform static timing analysis (STA), slack optimization, multi-corner / multi-mode timing closure
  
• Handle parasitic extraction, IR drop / electromigration checks, signal integrity analysis
  
• Use physical verification tools for DRC, LVS, and ensure design manufacturability (signoff)
  
• Develop and maintain scripts / automation (TCL, Perl, Python) to improve flow efficiency
  
• Resolve tool or flow-related issues in collaboration with EDA/CAD teams
  
• Document design decisions, present technical reviews to cross-functional teams

Preferred candidate profile

• Bachelors / Master’s degree in Electrical/Electronics, VLSI, ECE, or similar field
  
• Strong experience in physical design of digital logic (ASIC / CPU / GPU / SoC)
  
• Hands-on experience with PD / EDA tools such as:
  • Synopsys ICC2 / Fusion / IC Compiler • Cadence Innovus / Encounter / Tempus • Synopsys PrimeTime (STA) • Calibre / IC Validator (DRC / LVS / signoff) • Parasitic extraction tools (StarRC, QRC)
• Good understanding of PPA tradeoffs, timing closure, multi-corner / multi-mode (MCMM) flows
  
• Experience with power analysis, IR drop, EM checks
  
• Scripting skills: TCL, Perl, Python (for automation)
  
• Problem-solving mindset, ability to debug tool/flow issues