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Physical Design Engineer

Physical Design Engineer

Silicon Image India Research Development

12 - 17 years

2 - 6 Lacs

Pune

Posted:4 months ago| Platform:

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Skills Required

ASIC Semiconductor DFT Power management FPGA Perl Customer service Floor planning Physical design Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.

Responsibilities & Skills

Lattice Semiconductor is seeking a Sr. Staff Physical Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow.

Role specifics:

This is a full-time individual contributor position located in Pune, India.
The qualified candidate will be implementing and lead RTL to GDSII flow for complex design.
The qualified candidate will work and lead one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning, timing and physical signoff
The qualified candidate is expected to have experience in physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS).
The qualified candidate is expected to drive efficiency and quality of physical design flow and methodology and work together with internal EDA team and external tool vendors
The qualified candidate is expected to have scripting knowledge or perl /python etc to improve design efficiency and methodology development.
Collaborate with RTL, DFT , verification and full chip teams to ensure robust design implementation.
The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student.

Accountabilities:

Serve as a key contributor to FPGA design efforts.
Drive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area.
Ensuring design quality through all physical design quality checks and signoff.
Develop strong relationships with worldwide teams.
Mentor and develop strong partners and colleagues.
Occasional travel as needed.

Required Skills:

BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.
12+ years of experience in driving physical design activities of ASIC blocks and full chip.
Must have experience of multiple tapeouts
Experience on working with industry standard physical design tools including Innovus, Genus, Tempus, voltus, calibre, conformal etc.
Independent worker with demonstrated problem-solving abilities.
Proven ability to work with multiple groups across different sites and time zones

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.

Lattice

Feel the energy.

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Silicon Image India Research Development

Semiconductors / Technology

Bangalore

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Physical Design Engineer