Physical Design Engineer (Backend Signoff and Reliability)

Texas Instruments

2 - 6 years

0 Lacs

karnataka

Posted:1 week ago| Platform: Shine logo

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Skills Required

reliability design routing drc perc lvs esd pegasus pvs backend signoff power grid planning innovus tool custom routing signal power bump planning emir sigem cell em latupup cadence tools voltus tempus

Work Mode

On-site

Job Type

Full Time

Job Description

Role Overview: As a Physical Design Engineer at Texas Instruments Incorporated (TI), you will be a part of the Embedded Processor Group, focusing on Backend Signoff and Reliability. You will play a crucial role in the Power Grid planning and design at Chip level, utilizing hands-on experience in Innovus tool for custom routing to meet stringent integration requirements. Your responsibilities will also include Signal and Power bump planning and routing, as well as working on full chip EMIR, SigEM, and Cell EM. Additionally, you will be involved in Backend Signoff flows such as DRC, PERC, LVS, Latup-Up, ESD, and have hands-on experience in Cadence tools like Innovus, Voltus, Tempus, and Pegasus/PVS. Key Responsibilities: - Power Grid planning and design at Chip level - Utilize Innovus tool for custom routing to meet stringent integration requirements - Signal and Power bump planning and routing - Work on full chip EMIR, SigEM, and Cell EM - Implement Backend Signoff flows including DRC, PERC, LVS, Latup-Up, ESD - Hands-on experience in Cadence tools like Innovus, Voltus, Tempus, and Pegasus/PVS Qualifications Required: - 2-5 years of relevant experience - Proficiency in Innovus tool for custom routing - Familiarity with Backend Signoff flows such as DRC, PERC, LVS, Latup-Up, ESD - Hands-on experience with Cadence tools like Voltus, Tempus, and Pegasus/PVS (Note: About TI section has been omitted as it contains general information about the company and is not directly related to the job role),

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