Role & responsibilities Mirabilis Design is seeking a Performance Modeling Engineer with a deep understanding of computer architecture to explore and optimize the performance of processor cores, interconnects, and memory subsystems. The ideal candidate will be passionate about architecture-level performance analysis, with a strong theoretical foundation in pipelines, caching, and communication networks. The selected candidate will develop system-level models of emerging electronics standards to cycle-accurate details. This will include a clear understanding of computer architecture, how pipelines work, identify where there are latencies, power consumption of a semiconductor or electronics device, processor pipelines, interconnect, interfaces and memories. The models will be constructed using a combination of VisualSim Architect, VisualSim Script, Java and SystemC. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 3+ years of experience in architecture modeling, simulation, or performance analysis of compute systems. Strong understanding of: Processor pipelines (in-order, out-of-order) Cache coherency and memory hierarchies (L1-L3, shared memory) On-chip interconnects (AMBA, NoC, mesh) Queuing theory and throughput/latency trade-offs Experience with one or more simulation tools (e.g., VisualSim Architect, Gem5, SystemC, Simics, etc.) Proficient in C/C++, Python, and scripting for model development and automation. Preferred candidate profile The preferred candidate must have developed performance or power models in the last two or three years. They should be aware of key concepts of systems and semiconductors, in theory. Also, they should understand the pipeline, knowledge of queuing theory, power consumption, and good programming skills. It is preferred they understand and have worked on interconnects (NoCs, AXI bus), Processors (Cortex, Power, RISC-V), Memory Controllers (Synopsys or Cadence), DDR Memory, custom accelerators such as GPU, NPU and AI engines. For recent graduates, they must have done at least one simulation project in class or in an internship. Develop system-level performance models for CPUs, memory hierarchies, and on-chip networks using tools such as VisualSim Architect. Evaluate architecture trade-offs, identify bottlenecks, and propose optimizations for throughput, latency, and power efficiency. Analyze performance of workloads and task schedules across complex compute architectures including CPUs, GPUs, and NPUs. Work closely with hardware architects, software teams, and product managers to guide design decisions. Contribute to the development and validation of simulation libraries and reusable IP models. Preferred Qualifications Experience with ARM architecture, CMN-600, or Arteris NoC. Exposure to machine learning accelerators or heterogeneous SoCs. Familiarity with power modeling and thermal constraints at system level. Experience working with task schedulers or real-time systems.
