PCIe Architect

Job Description

Key Skills: Architect, System Verilog, Verilog, PCI Roles and Responsibilities: Architecture Design: Develop and optimize PCIe architectures for high-performance SoC designs, including switches, interconnects, and communication protocols. Protocol Expertise: Design and implement PCIe solutions that support various communication protocols such as PCIe, CXL, and AMBA/AXI. System Understanding: Contribute to overall SoC design by ensuring seamless communication between various IP blocks and subsystems. Performance Analysis: Conduct detailed performance analysis and benchmarking of PCIe designs to identify bottlenecks and improvement areas. Collaboration: Work closely with hardware, software, and verification teams to meet system and performance requirements. Troubleshooting: Identify and resolve complex PCIe design and simulation issues. Research and Development: Stay updated on PCIe specifications; contribute to new standards, methodologies, and tools. Engage in research projects to explore new PCIe programs and protocols. Skills Required: Primary Skills: Proficient in PCIe design and optimization techniques Strong understanding of digital design principles and SoC architecture Experience with Verilog and SystemVerilog Knowledge of RTL simulation tools and verification environments (e.g., Cadence, Synopsys, UVM) Expertise in PCIe, CXL, and AMBA/AXI protocols Soft Skills: Excellent problem-solving and analytical abilities Strong communication and collaboration skills Ability to work independently and within a team High attention to detail and quality focus Passion for research and innovation Preferred Skills: Experience with PCIe Gen-4/5/6 protocols Knowledge of ASIC design flows Familiarity with scripting languages (e.g., Python, Perl) Experience with version control systems (e.g., DesignSync, Git) Background in PCIe architecture, SerDes concepts, and low-power design Experience with synthesis tools (DC/DC-NXT, Fusion Compiler) Understanding of synthesis constraints and timing (STA) Experience with Spyglass (Lint, DFT, PM, CLK/RST, CDC/RDC) Formal verification using tools like Formality or Conformal LEC Publication history in technical journals or IEEE conferences is a plus Education: Bachelor's or Master's degree in Engineering or a related field