Lead Solutions Engineer

You will be responsible for understanding and reviewing design specifications to develop verification strategies, test plans, and coverage plans. Your role will involve creating constrained random verification environments, verification components, and writing tests, sequences, functional coverage, and assertions to achieve verification goals. Additionally, you will be developing C-based test cases for SOC verification. To excel in this role, you must have a strong background in functional verification fundamentals, environment planning, test plan generation, and environment development. Experience with System Verilog and UVM-based functional verification environment development is essential. Proficiency in verilog, VHDL, C, C++, Perl, and Python is required. Expertise in AMBA protocols (AXI/AHB/APB) and familiarity with protocols such as USB, PCIE, Ethernet, DDR, LPDDR, as well as version control and load sharing software are necessary. Desirable skills include prior experience with Cadence tools, ARM/CPU architectures familiarity, assembly language programming experience, knowledge of protocols like UART, I2C, SPI, JTAG, embedded C code development and debug, and formal verification experience. Excellent vocabulary, communication, organizational, planning, and presentation skills are essential for this role. You should be able to work independently, deliver high-quality results in a fast-paced environment, and be open to learning new methodologies, languages, and protocols. A self-motivated approach, willingness to take on additional responsibilities, and a commitment to personal development are key traits required to contribute to the team's success.,