Lead Design Verification

About the Role:

We are seeking an experienced Design Verification Engineer with 5 to 10 years of hands-on experience in verifying complex digital designs, particularly in IP cores, SoCs, and PCIe protocols. The ideal candidate will have deep expertise in developing and executing verification plans, writing testbenches, and automating verification environments to ensure high-quality silicon delivery.

Key Responsibilities:

• Develop and implement comprehensive verification plans and strategies for IP, SoC, and PCIe blocks.
  
• Create and maintain advanced verification environments using SystemVerilog, UVM (Universal Verification Methodology), and other relevant methodologies.
  
• Write and debug directed and random testcases, testbenches, and assertions (SVA/PSL).
  
• Collaborate with RTL design, architecture, and firmware teams to understand design specifications and requirements.
  
• Perform functional coverage analysis and closure; identify gaps and drive verification closure.
  
• Use simulators and formal verification tools to validate design correctness and performance.
  
• Participate in code reviews and provide feedback to improve quality and standards.
  
• Debug design and test failures, analyze root causes, and propose fixes.
  
• Drive automation of regression tests and integrate verification flows into CI/CD pipelines.
  
• Mentor junior engineers and contribute to team knowledge sharing and process improvement.
  

Required Skills and Experience:

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.
  
• 5 to 10 years of experience in design verification of complex digital IPs and SoCs, with a focus on PCIe and related high-speed interfaces.
  
• Strong proficiency in SystemVerilog and UVM for verification environment development.
  
• Experience with verification tools such as Mentor Questa, Cadence Incisive/Xcelium, Synopsys VCS, or similar.
  
• Deep understanding of PCIe protocol (Gen3/Gen4/Gen5) and experience verifying PCIe IPs or subsystems.
  
• Expertise in coverage-driven verification, functional coverage, assertions, and constrained random testbench development.
  
• Familiarity with scripting languages like Python, Perl, or TCL for automation.
  
• Knowledge of SoC design flows, integration challenges, and cross-functional verification.
  
• Experience with hardware emulation, FPGA prototyping, or formal verification is a plus.
  
• Strong problem-solving skills and attention to detail.
  
• Excellent communication skills and ability to work effectively in a team environment.

  Role & responsibilities

Preferred candidate profile