IO Layout Engineers

4 - 8 years

0 Lacs

Posted:1 week ago| Platform: Shine logo

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Work Mode

On-site

Job Type

Full Time

Job Description

As an IO Layout Engineer at our company, you will play a crucial role in the layout design of IO blocks such as GPIO, Analog IOs, High-Speed IOs, and Pad ring. Your responsibilities will include: - Working on IO layout for ASIC controllers under the guidance of senior team members. - Collaborating closely with designers to understand design constraints and create quality layout efficiently. - Managing all the Sign Off PV & quality checks on an IP layout. To excel in this role, you are required to meet the following qualifications and requirements: - Hold a Bachelor's or Master's degree in Electronics & Communication/Electrical engineering. - Possess 4 to 8 years of working experience in IO layout. - Have hands-on experience in layout design of IO blocks. - Experience in high-speed, low-power mixed-signal IPs is a plus. - Familiarity with TSMC 5nm layout (or below) using Virtuoso EXL features. - Expertise in Totem EMIR & Self-heating effects, Star RC extraction, and Calibre PV checks. - Good understanding of layout fundamentals such as Matching, EM, ESD, Latch up, coupling, crosstalk, etc. - Proficiency in top-level floorplan and hierarchical layout methodologies. - Possess good verbal and written communication skills. Candidates with only memory/Standard Cell layout experience are not relevant to this requirement. Join us and be part of a dynamic team where your skills and expertise in IO layout will be valued and utilized effectively.,

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