GPIO Circuit Design Engineer

Globalfoundries

6 - 11 years

8 - 13 Lacs

bengaluru

Posted:-1 days ago| Platform:

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Skills Required

fabrication vhdl semiconductor assurance simulation circuit designing project management analog verilog physical verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

Introduction: This position is for IO Design Engineer who will own End-to-End development of IO IPs. The successful candidate needs to have an exceptional background in CMOS design, End-to-end Analog/IO IP development experience, and needs to be a team player with a solution-oriented approach.

Essential Responsibilities:

Responsible for the development and delivery of IO IPs (GPIO, LVDS, SSTL, HSTL, MIPI, etc) in multiple technology nodes and achieving corresponding PPA indicators
Responsible for collaborating to defining IO IP architecture design and circuit design, simulation verification and reliability assurance
Collaborate in the design and implementation of test chips, packaging design, test board design, post-silicon testing, and qualification
Participate in market competition analysis and product definition
Supervise layout engineers and ensure the delivery of high quality layouts
Drive a culture of innovation

Other Responsibilities:

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Required Skills & Qualifications:

Bachelors or masters degree in electrical engineering, Electronics, or related field.
6+ years of experience in semiconductor IP design
Deep understanding of digital and mixed-signal IO design principles.
Knowledge of process technology impact on circuit design is a plus
High Speed I/O Design is also plus.
Experience with RTL design (Verilog/VHDL), synthesis, and timing closure.
Familiarity with ESD, pad ring design, and physical verification flows.
Strong project management and communication skills.
Experience with silicon validation and lab debug tools is a plus.

Preferred Qualifications:

Prior experience managing GPIO or similar IO IP blocks.
Knowledge of low-power design techniques and IO reliability.

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