Work from Office
Full Time
Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Experience (years) : 5+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent
Mirafra
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
My Connections Mirafra
Bengaluru, Hyderabad, Noida
5.0 - 7.0 Lacs P.A.
Ahmedabad, Bengaluru
7.0 - 11.0 Lacs P.A.
Noida
8.0 - 10.0 Lacs P.A.
Hyderabad
13.0 - 14.0 Lacs P.A.
13.0 - 18.0 Lacs P.A.
14.0 - 19.0 Lacs P.A.
4.0 - 6.0 Lacs P.A.
Bengaluru, Kochi, Hyderabad
7.0 - 17.0 Lacs P.A.
12.0 - 16.0 Lacs P.A.
4.0 - 6.0 Lacs P.A.