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VHDL Scan Insertion ATPG SDF simulation Cadence Tools DFT Engineering

Work Mode

On-site

Job Type

Full Time

Job Description

Roles and Responsibilities Develop RTL code using Verilog/VHDL Work with Mentor DfT tools and Cadence tools for design and verification Perform scan insertion, JTAG, ATPG DRC, and coverage analysis Debug simulations using timing and SDF Contribute to LBIST and Mixed Signal Radar IC-related projects (preferred) Investigate simulation failures and perform root cause analysis Collaborate with cross-functional teams; work independently and proactively Communicate effectively with both written and verbal communication

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Shashwath Solution
Shashwath Solution
www.shashwathsolutions.com

Information Technology

Bangalore

50-100 Employees

661 Jobs

    Key People

  • Amit Sharma

    CEO

  • Sneha Rao

    CTO

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