6.0 - 8.0 years

6 - 8 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Roles and Responsibilities Develop RTL code using Verilog/VHDL Work with Mentor DfT tools and Cadence tools for design and verification Perform scan insertion, JTAG, ATPG DRC, and coverage analysis Debug simulations using timing and SDF Contribute to LBIST and Mixed Signal Radar IC-related projects (preferred) Investigate simulation failures and perform root cause analysis Collaborate with cross-functional teams; work independently and proactively Communicate effectively with both written and verbal communication

Posted 1 month ago

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