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8.0 - 12.0 years
35 - 60 Lacs
bengaluru
Work from Office
About the role: Were looking for DFT Engineers across various experience levels (8 to 12years) to be part of our cutting-edge semiconductor design team. If you're skilled in Scan Insertion, ATPG, MBIST, IJTAG, or Hard IP Test Simulations, we have the perfect opportunity for you! Responsibilities MBIST insertion & pattern generation for SoC-level Memory repair flow integration Debugging MBIST in zero delay & SDF modes Automation using Perl, Python, Shell, or TCL
Posted 1 day ago
6.0 - 8.0 years
6 - 8 Lacs
Bengaluru / Bangalore, Karnataka, India
On-site
Roles and Responsibilities Develop RTL code using Verilog/VHDL Work with Mentor DfT tools and Cadence tools for design and verification Perform scan insertion, JTAG, ATPG DRC, and coverage analysis Debug simulations using timing and SDF Contribute to LBIST and Mixed Signal Radar IC-related projects (preferred) Investigate simulation failures and perform root cause analysis Collaborate with cross-functional teams; work independently and proactively Communicate effectively with both written and verbal communication
Posted 6 months ago
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