Work from Office
Full Time
Key Skills: Design Engineer, EJTAG Roles and Responsibilities: DFT architecture development and implementation ATPG, MBIST, and EJTAG-based test insertion and verification Pattern generation and coverage improvement Post-silicon debug and yield analysis Collaboration with STA and Physical Design teams for timing closure in DFT modes Potential interaction with external customers Supervise or guide team members as needed Skills Required: In-depth knowledge of DFT concepts Hands-on experience in ATPG, MBIST, and JTAG Experience in DFT insertion, pattern generation, vector simulation, and coverage improvement Strong debugging and problem-solving abilities Proficiency in scripting (Perl, Shell, etc.) Experience with industry-standard DFT tools: Mentor Graphics (TestKompress, Fastscan) or Synopsys (DFTMax, Tetramax) Proven experience working with geographically distributed teams Strong communication skills and ability to work independently Education: Bachelor's degree in Engineering with 8+ years of relevant experience Master's degree with 6+ years of relevant experience
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