4 Dft Design Jobs

THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

Lead and manage the DFT team responsible for delivering comprehensive DFT solutions for complex SoCs. Take end-to-end ownership of the DFT lifecycle - from architecture definition to silicon bring-up and production ramp. Collaborate cross-functionally with architecture, design, and physical design teams to ensure optimal testability integration. Define and track DFT milestones, quality metrics, and progress, ensuring alignment with program schedules and quality standards. Represent DFT in program and customer meetings, communicating status, risks, and mitigation plans. Architect and guide the implementation of DFT features, including Scan chain insertion and optimization, Test compression techniques, LBIST/MBIST (including repair logic), Boundary scan structures Lead efforts in performing DFT rule checks (DFT DRC) at RTL and netlist levels to ensure compliance with internal and industry standards. Use industry-standard EDA tools (e.g., Cadence, Siemens/Tessent) for DFT Design, DRC, Pattern Generation and work with EDA/Internal CAD team for tool/flow improvements Drive DFT pattern generation and validation, including gate-level simulations with and without SDF. Partner with the verification team to define and execute DFT verification plans. Collaborate with physical design and STA teams to implement DFT constraints and strategies for synthesis and timing closure. Analyze silicon test data, debug test failures, and work with the test engineering team to resolve bring-up and production issues. Provide technical leadership, mentorship, and career development for DFT engineers on the team. Qualifications and Experience: Proven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up. Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs. Strong team management and leadership experience with a track record of mentoring and growing engineering talent. Bachelors or Master s degree in Electrical/Electronics Engineering or a closely related field. 12+ years of hands-on experience in DFT methodologies and industry-standard test techniques. Deep knowledge and hands-on experience with: Logic BIST (LBIST) Automatic Test Pattern Generation (ATPG) DFT Rule Checks (DFT DRC) Scan chain compression and stitching Low-power DFT techniques and constraints Memory BIST (MBIST) including repair mechanisms Boundary Scan (IEEE 1149.1) Analog DFT strategies JTAG architecture and TAP integration DFT-specific STA constraints Proficient in using industry-standard DFT EDA tools, including cadence, Siemens. Strong scripting and automation skills using Perl, Tcl, and/or Python. Solid understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow. Excellent problem-solving skills, with the ability to troubleshoot and resolve complex DFT issues efficiently. Strong communication and interpersonal skills, capable of working effectively in cross-functional and team-oriented environments.

Key Skills: Design Engineer, EJTAG Roles and Responsibilities: DFT architecture development and implementation ATPG, MBIST, and EJTAG-based test insertion and verification Pattern generation and coverage improvement Post-silicon debug and yield analysis Collaboration with STA and Physical Design teams for timing closure in DFT modes Potential interaction with external customers Supervise or guide team members as needed Skills Required: In-depth knowledge of DFT concepts Hands-on experience in ATPG, MBIST, and JTAG Experience in DFT insertion, pattern generation, vector simulation, and coverage improvement Strong debugging and problem-solving abilities Proficiency in scripting (Perl, Shell, etc.) Experience with industry-standard DFT tools: Mentor Graphics (TestKompress, Fastscan) or Synopsys (DFTMax, Tetramax) Proven experience working with geographically distributed teams Strong communication skills and ability to work independently Education: Bachelor's degree in Engineering with 8+ years of relevant experience Master's degree with 6+ years of relevant experience

As a DFT Technical Lead , you will be responsible for overseeing the DFT implementation and verification activities for complex SoCs/ASICs, collaborating with cross-functional teams and architects. Your role will involve leading teams technically, providing training and mentoring, and interfacing with customers. Under general supervision, you will engage in engineering work, applied research, and the development/design of new integrated chips, including architectural design, logic design, circuit design, physical design, verification, fabrication, and packaging. Roles & Responsibilities: Hands-on expertise in Full Chip SCAN , Compression , MBIST , ATPG , and other DFT-related skills. Over 10 years of experience, with strong hands-on involvement in full chip DFT design , implementation , vector generation/verification , JTAG , boundary scan , and simulation . Proficient with Scan , Compression , ATPG , and simulation tools such as Mentor , Synopsys , or Cadence . Knowledge of Logic BIST is a plus. Proven track record of participation in successful tape-outs of SoC/ASIC chips at 14nm or below, consistently meeting test targets. Strong understanding of front-end SoC/ASIC design and implementation, including Synthesis and Static Timing Analysis (STA) . Experience in developing and automating flows and scripts in Perl/Tcl to enhance DFT methodologies and processes. Excellent problem-solving , debugging , and proactive approach to challenges. Demonstrated leadership in mentoring/training junior teams , managing projects, and taking on technical leadership roles. Strong customer interaction , communication , and teamwork skills.