10 Dft Design Jobs

Minimum qualifications: Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience. 3 years of experience in DFT design or CAD. Experience with DFT EDA tools like Tessent. Experience with scripting in languages like Python and Tcl. Experience in developing and maintaining DFT flows and methodologies. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field. Experience in advanced technology nodes. Experience with DFT for a medium to complex subsystem with multiple physical partitions. Experience with developing software pipelines for managing large-scale engineering data and...

Key Skills: DFT, DFT Design, Scan Insertion, ATPG, MBIST Roles and Responsibilities: Develop and implement DFT strategies including scan compression and insertion, Memory BIST, and Logic BIST. Conduct at-speed testing and fault simulation to ensure product quality. Perform back-annotated gate-level verification and silicon debug. Utilize Verilog RTL, TCL, and/or Perl for coding tasks. Work proficiently in Unix/Linux environments. Collaborate with cross-functional teams to integrate DFT solutions into designs. Stay updated with industry standards such as IEEE 1149, 1500, 1687, and 1838. Engage in continuous learning and application of new DFT methodologies and tools. Skills Required: Strong e...

Key Responsibilities: Implement and verify DFT logic including MBIST, scan chains, scan compression, TAP, iJTAG, and eFuse. Perform scan insertion, ATPG pattern generation, and coverage analysis. Execute MBIST insertion, simulation, and debug at RTL and gate levels. Collaborate with silicon and test engineering teams to create test plans and generate test patterns. Participate in post-silicon bring-up, diagnostics, and characterization activities. Work with EDA and IP vendors to adopt advanced DFT/DFD/DFY methodologies. Integrate DFT/BIST flows into synthesis and ensure timing closure across all stages. Utilize Verilog HDL, simulation, and waveform debugging tools for design verification. Ap...

We’re hiring a DFT Lead with 10+ years of experience in VLSI front-end design. The role involves DFT architecture, ATPG, scan insertion, STA, timing closure, and debug. Strong scripting and communication skills are essential. Required Candidate profile Experienced DFT professional skilled in ATPG, scan insertion, and timing closure. Proven ability to lead design-for-test implementation and debugging in complex SoC environments using industry tools.

Key Skills: Scan Insertion, DFT, MBIST, ATPG, JTAG, DFT Design Roles and Responsibilities: Define DFT strategy, methodologies, and best practices across projects. Design DFT features, test structures, debug structures, and test plans. Create or guide the creation of test vectors to ensure coverage and compliance. Collaborate with the physical design team to meet DFT requirements. Validate that post-Physical Design (PD) implementations adhere to DFT needs. Partner with designers to increase test coverage, debug observability, and design flexibility. Verify that all DFT requirements are successfully integrated and functional. Work closely with verification engineers to perform tests and debug ...

As a DFT Design Engineer at our company, your role will involve working on DFT design from unit level to chip level, encompassing all aspects of DFT design functions such as scan, MBIST, and ATPG. You will have opportunities to contribute in the areas of CPU and SOC DFT design and verification. Key Responsibilities: - Define DFT strategy and methodologies - Design the DFT features - Define test structures, debug structures, and test plans - Create test vectors or oversee their creation - Collaborate with the physical design team to meet requirements - Validate DFT requirements are being fulfilled - Work with designers to enhance test coverage, debug observability, and flexibility - Verify po...

THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate ...

Lead and manage the DFT team responsible for delivering comprehensive DFT solutions for complex SoCs. Take end-to-end ownership of the DFT lifecycle - from architecture definition to silicon bring-up and production ramp. Collaborate cross-functionally with architecture, design, and physical design teams to ensure optimal testability integration. Define and track DFT milestones, quality metrics, and progress, ensuring alignment with program schedules and quality standards. Represent DFT in program and customer meetings, communicating status, risks, and mitigation plans. Architect and guide the implementation of DFT features, including Scan chain insertion and optimization, Test compression te...

Key Skills: Design Engineer, EJTAG Roles and Responsibilities: DFT architecture development and implementation ATPG, MBIST, and EJTAG-based test insertion and verification Pattern generation and coverage improvement Post-silicon debug and yield analysis Collaboration with STA and Physical Design teams for timing closure in DFT modes Potential interaction with external customers Supervise or guide team members as needed Skills Required: In-depth knowledge of DFT concepts Hands-on experience in ATPG, MBIST, and JTAG Experience in DFT insertion, pattern generation, vector simulation, and coverage improvement Strong debugging and problem-solving abilities Proficiency in scripting (Perl, Shell, e...

As a DFT Technical Lead , you will be responsible for overseeing the DFT implementation and verification activities for complex SoCs/ASICs, collaborating with cross-functional teams and architects. Your role will involve leading teams technically, providing training and mentoring, and interfacing with customers. Under general supervision, you will engage in engineering work, applied research, and the development/design of new integrated chips, including architectural design, logic design, circuit design, physical design, verification, fabrication, and packaging. Roles & Responsibilities: Hands-on expertise in Full Chip SCAN , Compression , MBIST , ATPG , and other DFT-related skills. Over 10...