As a DFT Technical Lead , you will be responsible for overseeing the DFT implementation and verification activities for complex SoCs/ASICs, collaborating with cross-functional teams and architects. Your role will involve leading teams technically, providing training and mentoring, and interfacing with customers. Under general supervision, you will engage in engineering work, applied research, and the development/design of new integrated chips, including architectural design, logic design, circuit design, physical design, verification, fabrication, and packaging. Roles & Responsibilities: Hands-on expertise in Full Chip SCAN , Compression , MBIST , ATPG , and other DFT-related skills. Over 10 years of experience, with strong hands-on involvement in full chip DFT design , implementation , vector generation/verification , JTAG , boundary scan , and simulation . Proficient with Scan , Compression , ATPG , and simulation tools such as Mentor , Synopsys , or Cadence . Knowledge of Logic BIST is a plus. Proven track record of participation in successful tape-outs of SoC/ASIC chips at 14nm or below, consistently meeting test targets. Strong understanding of front-end SoC/ASIC design and implementation, including Synthesis and Static Timing Analysis (STA) . Experience in developing and automating flows and scripts in Perl/Tcl to enhance DFT methodologies and processes. Excellent problem-solving , debugging , and proactive approach to challenges. Demonstrated leadership in mentoring/training junior teams , managing projects, and taking on technical leadership roles. Strong customer interaction , communication , and teamwork skills.
