Design Verification- IP/DDR/USB

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MTS SILICON DESIGN ENGINEER

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THE ROLE:

The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs.

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THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

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KEY RESPONSIBILITIES:

• Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.
• Create methodology-based (UVM) verification testbenches and components from scratch for various IP features.
• Quality deliverables through regressions
• Verification coverage:code-coverage, functional coverage, assertions, to achieve 100% verification completeness
• Reviews, and feedback to design/architecture teams.

PREFERRED EXPERIENCE:

• Years of experience 9+ Required.
• Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA)
• Expertise in code and functional coverage.
• Excellent Problem solving and debugging skills.
• Excellent Communication skills
• Strong digital design knowledge.
• Exposure to UPF based low power RTL verification
• Prior experience in PLL verification and Mixed signal verification methodology is highly desirable.
• Exposure to digital-analog co-simulations (cosims) is desirable.

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ACADEMIC CREDENTIALS:

Bachelors orMastersdegree in computer engineering/Electrical Engineering