4 Test Bench Jobs

1) Plan and execute Engine CoP testing 2) Co-ordinate internal & external stakeholders for CoP selection 3) Responsible for clearance of tested parts & engines 4) Plan and monitor assets of engine CoP test equipments/instruments 5) Support to team in risk assessment and in critical topics 6) Report test result to management 7) Responsible for conversion and scrap reduction Quality assurance process in Engine CoP: 1) Execute Quality process in Engine CoP: 2) Execute activities control plan acc.to standards/ procedures/ authority specific requirements 3) Ensure adherence of processes(retro fitment, engine clearance) and control plan. 4) Arrange meeting with homologation team and update necessary documents/ plan activities accordingly. 5) Responsible for Managing of CoP folders and data 6) Responsible for payment clearance of test agency 7) Responsible for E sticker verification activities 8) Support to team in Issue resolution and work on action item 9) Support to team in failures investigation and work on action item.

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

Role & responsibilities Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for sophisticated products. Co-work with international colleagues on developing new verification flows to take on the challenges in design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Core Requirements Good communication skills and ability to work well in a team Guide new team members and energetic engineers in the team Analytical capability for complex CMOS and/or gate level circuit designs Proficient with either SPICE and/or Verilog simulations Qualifications & Skills Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience in AMS verification and co-sim Preferred candidate profile Immediate to Max 15 Days Joiner Perks and benefits

In your new role you will: Be in continuous and intensive contact with our development sites worldwide Advise and support the experts from our business units in verification projects Drive the internal exchange of know-how and experience at Infineon Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineon's design system and supporting their implementation in the development of new products Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan Design and develop the verification environment for ICs using the "Universal Verification Methodology" (UVM) Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach Use the Unified Power Format (UPF) to verify the low-power aspects of our designs You are best equipped for this task if you have: You have a degree in Electrical Engineering, Computer Science or a similar academic discipline. You have at least five years of professional experience in Metric Driven Verification (digital & mixed-signal) and Formal Verification. You have experience with microcontroller-based ICs and ideally with security and safety requirements. You are experienced in the creation and dissemination of methods in the area of functional verification. You have an excellent understanding of and application skills in UVM and UPF. You have sound knowledge of firmware and RTL design (VHDL) - experience with Cadence verification software is a plus. You have some initial experience in technical leadership and project management.