13 Test Bench Jobs

As an FPGA Designer in the Research and Development department, you will play a crucial role in defining and developing intricate FPGA designs for AWG & Digitizer products. Working in a dynamic and collaborative environment, you will closely collaborate with the R&D Project Manager, Product Architects, Solution Teams, Software Qualification, and Software Engineers to enhance existing products and introduce new offerings. Your ability to work effectively within a team, including other design teams based in the US & Europe, is essential for success in this role. Key Requirements: - A Bachelor's or Master's degree in Electrical / Electronic Engineering. - 8-10 years of hands-on experience in FPGA development with proficiency in Altera and Xilinx technologies. - Proficiency in RTL languages such as VHDL and Verilog. - Familiarity with Xilinx FPGA Tools Design Flow, including Vivado and Chipscope. - Experience in achieving timing closure for complex designs. - Proficiency in Functional Simulation tools like Synopsys, Mentor, Cadence, or Vivado simulator. - Ability to develop self-checking Simulation environments involving test benches, automation scripts, and test case creation. - Quick adaptability to new technologies and product segments. - Strong written communication skills for creating various technical documents. - Self-motivated, organized, and accountable individual. - Excellent team player with responsive communication skills. Preferred Skills: - Experience in high data throughput real-time processing (~ 1GSPS), PCIe, DDR memories, FSM, etc. - Familiarity with Test & Measurement lab equipment. - Knowledge of C/C++ programming languages. In this role, your expertise and dedication will contribute significantly to the advancement and innovation of FPGA designs for cutting-edge products.,

Role & responsibilities In this role you will perform product and process audit of machining process engine testing & engine assembly resolve & sustain internal & external customer complaints. Disposal of customer returned material & updation in SAP on a timely basis Ensuring the product & process audit of engine assembly & machining processes is conducted as per schedule Performing engine testing as per plan Resolving internal customer complaints PPM through analysis, corrective actions on a timely basis to ensure customer satisfaction New development parts / processes implementations as per plan Implementing manufacturing excellence initiatives related to product quality, cost, delivery; manufacturing efficiency and operational excellence to exceed customer expectations. Collaborating with internal and external stake holders, provide support for related activities to ensure timely implementation of different projects by proactively extending necessary information and support Preferred candidate profile

THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.?? THE PERSON: ? You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: ? Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystemVeriloglanguage Good working knowledge ofSystemCand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Makefile, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.?? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ MTS SILICON DESIGN ENGINEER ? ? THE ROLE: The candidate will get to work on the Verification of complex PLLs that are delivered to various AMD SoCs. ? THE PERSON: ? You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. ? KEY RESPONSIBILITIES: ? Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations. Create methodology-based (UVM) verification testbenches and components from scratch for various IP features. Quality deliverables through regressions Verification coverage:code-coverage, functional coverage, assertions, to achieve 100% verification completeness Reviews, and feedback to design/architecture teams. PREFERRED EXPERIENCE: ? Years of experience 9+ Required. Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions (SVA) Expertise in code and functional coverage. Excellent Problem solving and debugging skills. Excellent Communication skills Strong digital design knowledge. Exposure to UPF based low power RTL verification Prior experience in PLL verification and Mixed signal verification methodology is highly desirable. Exposure to digital-analog co-simulations (cosims) is desirable. ? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

KEY RESPONSIBILITIES: ? Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues? Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements ? PREFERRED EXPERIENCE: ? Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools? Proficient in using UVM test benches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++?? Graphics pipeline knowledge Developing UVM based verification frameworks and test benches, processes and flows Automating workflows in a distributedcomputeenvironment.?? Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts andSystem Veriloglanguage Good working knowledge ofSystem Cand TLM with some related experience.?? Scripting language experience: Perl, Ruby,Make file, shell preferred.?? Exposure to leadership or mentorship is an asset Desirableassetswith prior exposure to video codec system or other multimedia solutions.?? ? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

KEY RESPONSIBILITIES: Identify formal friendly modules/features across Data Fabric unit/subsystem and work with different stake holders in getting a thorough understanding of micro arch/high level spec and get clarification (if any). Evaluate cross-feature/cross-unit dependency impact. Populate detailed test plan (planned checks, abstraction, coverage) post feature analysis and get it reviewed & incorporate feedback. Create Formal Test bench with assertions/assumptions with necessary level of abstraction in place to verify a complete feature. Debug failures to root cause issues/fix constraints, deal with tool issues efficiently in collaboration with concerned AE from Synopsys/Cadence. On a need basis, work on Post-Si bug recreation. On a need basis, work on Flow automation related to Formal flow. PREFERRED EXPERIENCE: Prior experience on Formal verification on Complex IP's. Proficiency in overall Formal Verification methodology with tools like (VC-FORMAL/JASPER). Proficiency in creating test plans, building formal test benches from scratch. Good understanding about computer architecture/microarchitecture and ability to deal with complex sequential logic and data path. Good understanding of Verilog, System Verilog, SVA. Some knowledge of shell/perl/python scripting is a plus. Should have leadership quality, quick thinker, pro-active, adaptable & outspoken/approachable. Must communicate well both written and orally. Must be well-organized and should be able to multitask well with due diligence on closing his/her tasks. ACADEMIC CREDENTIALS: Bachelor's or master'sdegree in Electronics or Electrical or Computer engineering

As a Senior FPGA Design Engineer at Prodigy Technovations in Bangalore/Bengaluru, you will have the opportunity to work on existing and next-generation Protocol Analyzers and similar products. Your role will involve contributing to the entire FPGA-based product development flow, from requirement analysis to final product testing in a lab environment. Your responsibilities will include architecture/micro-architecture design, Verilog logic implementation for targeted FPGA, and writing test benches to validate the design. You will collaborate closely with board design, software, testing, and lab teams to ensure the product meets customer requirements. Additionally, you will work with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI, among others. Qualifications: - BE/ME in Electronics from a reputed college, with a specialization in VLSI and Embedded Design being a plus. - 3 to 8 years of experience in designing and implementing FPGA-based solutions in Xilinx or Altera FPGA, preferably in FPGA-based product development. - Experience in System Design with Xilinx/Altera FPGA devices and relevant tools. - Proficiency in Verilog and/or VHDL coding. - Experience in synthesis, implementation, and using constraints to achieve timing requirements. - Knowledge of high-speed FPGA designs and Static Timing Analysis (STA) is advantageous. - Experience in building test benches for verification, board-level testing, and system debugging. - Familiarity with protocols like UFS, UniPro, USB, Ethernet, PCIe, I3C, I2C, SPI, QSPI, UART, JTAG, SPMI, RFFE, SD, eMMC. - Hands-on experience with FPGA debugging tools, oscilloscopes, and Logic Analyzers. - Strong problem-solving and debugging skills. If you are a motivated and experienced FPGA Design Engineer with a passion for product development and a strong background in FPGA technologies, we encourage you to apply for this exciting opportunity. Join our team at Prodigy Technovations and be part of creating cutting-edge solutions for top semiconductor companies.,

Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

Role & responsibilities 7+ years of design verification experience. MS (or higher) in EE/EC/ECC Engineering As a member of the Design Verification [ Pre-Silicon DV ] Team for client WCS/SCE BU You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/ UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary

To support development,validation & optimization of powertrain systems including IEC,hybrid powertrains & EV drivetrains. Conducting lab & vehicle-level tests, analyzing performance data, ensuring systems meet regulatory and performance standards.

Job Description: Very important: Vehicle knowledge (the more the better) Knowledge of Driver assistant functions (ADAS, Powertrain, ) themselves as well as how they are supposed to work/what they should do Proper, fluent English in written and spoken form Interest in the Technology, Motivation, Discipline and Honesty Important: Knowledge in EXAM Testbench (HIL) knowledge Vehicle bus-protocol knowledge (not the details, just the broad idea what a bus is and how it is used for communication) Knowledge on ECU flashing guidelines and therefore knowledge of ODIS ControlDesk Knowledge Useful: German A2+ Python Willingness to travel for onsite training if necessary

1) Plan and execute Engine CoP testing 2) Co-ordinate internal & external stakeholders for CoP selection 3) Responsible for clearance of tested parts & engines 4) Plan and monitor assets of engine CoP test equipments/instruments 5) Support to team in risk assessment and in critical topics 6) Report test result to management 7) Responsible for conversion and scrap reduction Quality assurance process in Engine CoP: 1) Execute Quality process in Engine CoP: 2) Execute activities control plan acc.to standards/ procedures/ authority specific requirements 3) Ensure adherence of processes(retro fitment, engine clearance) and control plan. 4) Arrange meeting with homologation team and update necessary documents/ plan activities accordingly. 5) Responsible for Managing of CoP folders and data 6) Responsible for payment clearance of test agency 7) Responsible for E sticker verification activities 8) Support to team in Issue resolution and work on action item 9) Support to team in failures investigation and work on action item.

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment