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Design & Verification Engineer

4 - 8 years

6 - 10 Lacs

Noida

Posted:2 months ago| Platform: Naukri logo

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Skills Required

Verification Engineering VHDL Perforce design patterns C++ languages HDL languages Verilog System Verilog

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are not looking for superheroes, just super minds We seek a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with 4-8 years of significant experience in software development. Experience in EDA will be a plus! Proficiency in C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. Your understanding of HDL languages Verilog/VHDL/System Verilog is essential. We value your knowledge of scripting languages, hands-on knowledge of Revision control systems like Perforce will only improve the development time. Good analytical, abstraction and interpersonal skills will help in creating bigger and sustainable solutions for complex systems. Ability to work with multi-functional teams as a great teammate will help in creating good solutions that resolve actual customer issues. Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. Teammate and good management skills

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www.siemens.com

Automation Machinery Manufacturing

Munich Brande

10001 Employees

1885 Jobs

    Key People

  • Roland Busch

    President and Chief Executive Officer

  • Ralf P. Thomas

    Chief Financial Officer

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