Posted:None|
Platform:
Hybrid
Full Time
Strong understanding of computer architecture and logic design
->Knowledge of Verilog, system Verilog and UVM is a must->Strong understanding of state-of-the-art verification techniques, including assertion and constraint-random metric-driven verification->Define test plans, test benches, and tests using System Verilog and UVM->Working knowledge of C/C++ and Assembly programming languages->Exposure to scripting (python preferred) for post-processing and automation->Experience with gate level simulation, power and reset verification
Innominds Software
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