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Design For Testability Engineer, SSG

Design For Testability Engineer, SSG

Amazon

1 - 4 years

3 - 6 Lacs

bengaluru

Posted:2 weeks ago| Platform:

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Skills Required

automation dft vlsi static timing analysis chip design failure analysis perl system verilog uvm python

Work Mode

Work from Office

Job Type

Full Time

Job Description

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and reimagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.
Work hard. Have fun. Make history. At Amazon, DFT (Design-for-Testability) is a multi-faceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more. As a DFT Engineer, you will impact and see the device through its entire lifecycle, from definition stage to high volume production. You will be working in close collaboration with multiple VLSI engineering groups including design, verification, backend, test, reliability and more. As part of the chip design group, you will: Contribute to the design and verification of DFT logic and components Help to drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon Review sign-off level timing closure using static timing analysis of DFT modes Perform wafer probe testing, ATE testing, silicon bring-up, diagnosis and support for physical failure analysis Take high volume chips to production with high coverage ATE test program Bachelors degree in Electrical Engineering or a related field Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing Chip design experience in Verilog and System Verilog Chip verification experience, UVM methodology Scan insertion tools and methodologies MBIST and BISR, BIHR insertion tools and methodologies EFUSE controllers and related structures Top level DFT architecture definition experience Gate-level simulations Static timing analysis, DFT related timing closure Scripting (Perl/Tcl) Masters degree in Electrical or Communications Engineering or a related field Experience with formal verification techniques including abstraction and end-to-end checking Experience with ARM and various DSP ISAs Experience with industry standard tools and scripting languages (Python or Perl) for automation

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Design For Testability Engineer, SSG