Design Engineer 1

Tessolve is looking for an experiencedPhysical Design Engineerto join our team in Bangalore. The ideal candidate will have a strong background inRTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools forfloorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.

Key Responsibilities:

• End-to-endphysical design flow from RTL to GDSIIat advanced technology nodes (7nm, 5nm, or below).
• Floorplanning and Partitioning: Optimize chip area, power, and performance.
• Placement and CTS: Optimize standard cell placement, buffer insertion, and clock tree synthesis.
• Routing and Timing Closure: Work on congestion analysis, RC extraction, and static timing analysis (STA).
• Power Optimization: Implement low-power techniques such as clock gating, power gating, and multi-voltage domains.
• Physical Verification: Perform DRC, LVS, and Antenna checks using industry-standard tools.
• Sign-off Analysis: Work on IR drop, Electromigration (EM), and Signal Integrity (SI) analysis.
• Collaborate withRTL design, DFT, and verificationteams for design convergence.
• Debug and resolvetiming, power, and physical verification issues.

Required Skills:

• 4 to 8 yearsof experience inPhysical Design and Implementation.
• Strong knowledge ofEDA tools(Synopsys ICC2/Fusion Compiler, Cadence Innovus, or Mentor Olympus).
• Experience infloorplanning, power planning, placement, routing, and timing closure.
• Expertise inStatic Timing Analysis (STA)using Primetime or Tempus.
• Hands-on experience inphysical verification tools(Calibre, PVS, or Pegasus).
• Good understanding ofdesign constraints, clock tree optimization, IR drop, and power integrity.
• Experience withscripting (Tcl, Perl, Python)for automation is a plus.
• Strong problem-solving skills and ability to work in a fast-paced environment.

Preferred Qualifications:

• Experience with7nm, 5nm, or lower process nodes.
• Knowledge oflow-power design methodologies.
• Familiarity withmulti-power domain design (UPF/CPF-based flows).

Why Join Tessolve

• Opportunity to work on cutting-edge semiconductor technology.
• Exposure to advanced process nodes and complex designs.
• Collaborative and innovative work environment.
• Competitive salary and benefits.

If you are passionate aboutPhysical Designand looking for an exciting opportunity atTessolve, apply now!