Posted:1 month ago|
Platform:
Work from Office
Full Time
• Strong hands-on experience with SystemVerilog and UVM methodology.
• Solid knowledge of SoC/ASIC architecture and verification lifecycle.
• Hands-on experience in writing testbenches, stimulus, checkers, monitors, and
scoreboards .
• Strong debugging skills using simulation tools like VCS, Questa.
• Experience with functional and code coverage.
• Familiarity with Register Abstraction Layer (RAL) modeling and verification.
• Excellent analytical and problem-solving skills.
• Strong communication and teamwork abilities.
Thompsons Hr Consulting
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