CPU STA/Timing Analysis Engineer (All Levels)

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. As a Physical Design Timing Engineer, you will work with microarchitecture, RTL design, CAD, block level and top level physical design teams to run, analyze timing and drive timing closure. Roles and Responsibilities Work with design and DFT teams to understand, implement and validate constraints. Run SOC timing runs at all hierarchies Analyze timing and work with RTL/DFT teams to facilitate logic changes required. Feedback to block level and top level physical design engineers on key fixes required for timing closure. Work with CAD team to implement timing infrastructure. Create ECOs from timing runs to help timing closure. Document and help with timing methodology definition Preferred qualifications MS degree in Electrical Engineering; 10 years of practical experience Experience in timing flows with industry standard tools. Experience in all aspects of timing closure for multi-clock domain designs. Experience in deep submicron process technology nodes is strongly preferred. Experience with STA on large SOC with multi-scenario timing closure. Experience with Timing ECO techniques and implementation. Knowledge of library cells and optimizations. Familiar with circuit modeling, transistor fundamentals and worst case corner selection. Solid understanding industry standard tools for synthesis, place & route and tapeout flows. Good communication skills to work with different teams to accurately describe issues and follow them through for completion. Experience in STA and timing closure of high-performance SOC designs in sub-micron technologies. Knowledge of all aspects of timing including noise, cross-talk and others. Knowledge of basic SoC architecture and HDL languages like Verilog.