CPU Digital Design Manager, Silicon

Role Overview: You will be part of a team that is focused on developing custom silicon solutions to power Google's direct-to-consumer products. Your contributions will play a crucial role in shaping the future of hardware experiences, enhancing performance, efficiency, and integration for products loved by millions globally. Key Responsibilities: - Lead, mentor, and manage a team of ASIC RTL Engineers responsible for integrating and delivering critical SoC sub-systems like CPU, GPU, HSIO, and LSIO. - Provide technical leadership and ownership for the sub-systems from microarchitecture definition to tape-out and silicon bring-up. - Drive project execution by planning tasks, setting priorities, conducting code and design reviews, and overseeing the development of complex features and logic. - Collaborate with SoC architects to interpret specifications and develop robust implementation strategies meeting stringent Power, Performance, and Area (PPA) goals for premium-tier mobile products. - Act as the primary design interface for cross-functional teams, including Verification, Physical Design, DFT, and Software/Firmware, ensuring seamless integration and resolving technical challenges. Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - 15 years of experience leading design teams. - Experience in one or more of the following sub-systems: CPU cores (e.g., ARM), GPU graphics processors, HSIO protocols (e.g., PCIe, UFS, LPDDR), or LSIO peripherals. Preferred Qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, focusing on computer architecture. - Proficiency with modern ASIC design methodologies and tools for front-end quality checks such as Lint, CDC/RDC, Synthesis, and power-aware design using UPF. - Understanding of the complete SoC design lifecycle and the interplay between front-end design, verification (DV), DFT, and physical design (PD).,