C++ Market Data Developer

Role & responsibilities

Senior C++ Low-Latency Market Data Engineer

Positions: 5

Location: Chennai, Siruseri

Experience: 4-12 years

Must Have:

Role Summary

green-field initiative

You will work in a distributed, highly skilled engineering team across two locations, shaping a system built for speed, quality, and long-term maintainability.

What You Will Do

• Design and develop core components of the low-latency Market Data platform.
• Implement and optimize feed handlers over TCP and multicast UDP binary protocols.
• Work with feeds such as ITCH, SBE, FAST, FIX, and venue-specific formats.
• Work on L1, L2, and L3 order-book construction, conflation, correlation, consolidated tapes, and replay pipelines.
• Optimize performance by focusing on:
• CPU cache hierarchies and memory locality
• NUMA-aware design and predictable execution
• Data-structure layout and allocation-free paths
• Branch prediction, prefetching, TLB behavior
• NIC tuning and kernel network stack optimization
• Build and maintain high test coverage, including latency regression and deterministic behavior tests.
• Validate correctness and quality of Market Data flows end-to-end.
• Perform profiling and instrumentation using eBPF, perf events, and flame graphs.
• Analyze binary protocol dumps and low-level hexdump traces for debugging.
• Deploy, test, and validate software in QA and Production environments.
• Participate in on-call and incident support once the platform is in production.
• Contribute to documentation, knowledge sharing, and continuous improvement.

What You Bring

Experience

• 8+ years of professional experience with modern C++ (C++14/17/20).
• 5+ years working directly in Market Data or trading low-latency systems.

Technical Skills

• Deep experience integrating exchange Market Data protocols: TCP, multicast UDP, ITCH, SBE, FAST, FIX.
• Experience with L1/L2/L3 order books, conflation, correlation, replay, and consolidated feeds.
• Mastery of modern C++ techniques including:
• advanced templates
• lock-free and wait-free structures
• concurrency and memory models
• Strong Linux expertise:
• CLI and low-level tooling (perf, strace, tcpdump, sar, iostat)
• understanding of system calls, CPU scheduling, memory management
• Understanding of modern CPU microarchitecture: cache hierarchies, NUMA, branch prediction, prefetching, TLB behavior.
• Experience with low-latency NICs (Solarflare, Mellanox), driver settings and tuning.
• Familiarity with kernel-bypass technologies (DPDK, Onload) or advanced NIC/driver tuning is a strong plus.
• Experience with low-overhead instrumentation and performance profiling (eBPF, perf events, flame graphs).
• Strong focus on reliability, defensive coding, and graceful failure handling.
• Ability to analyze binary protocol dumps and low-level hexdump traces.
• Strong hands-on experience with Python / Go (mandatory).
• Experience with Git/GitLab, Linux shell scripting, CI/CD.
• Knowledge of Ansible is a plus.
• Clear communication skills and ability to work in a distributed team.

Nice to Have

• Understanding of hardware timestamps, PTP, and time-synchronization pipelines.
• Experience with Elastic, Grafana, Prometheus.

Preferred candidate profile

Siruseri, Chennai, or someone ready to relocate.