Associate III - VLSI-PNR-Aster

Role Overview: As a Physical Design Engineer at UST, you will be expected to have a strong understanding of the Basic Fundamentals of C-MOS technology and a comprehensive knowledge of the PD Flow for flat and hierarchical designs. Your responsibilities will include independently handling RTL/Netlist to GDSII conversions at block level/SS/SoC and executing multiple tape outs with a focus on low power implementation. Experience in floor planning, partitioning, integration at Subsystem/Chip, and hands-on exposure to lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, etc., will be crucial. You will also be involved in floor planning, placement optimizations, clock tree synthesis (CTS), routing, block/top-level signoff STA, physical verification checks (DRC/LVS/ERC/antenna), and other reliability checks (IR/EM/Xtalk). Expertise in industry-standard EDA tools from Synopsys, Cadence, and Mentor is essential, along with exposure to DMSA flow for ECO generation and implementation. Additionally, a good understanding of VLSI processes and proficiency in scripting with TCL and Perl will be required. Key Responsibilities: - Strong understanding of Basic Fundamentals of C-MOS technology - Comprehensive knowledge of PD Flow for flat and hierarchical designs - Independently handle RTL/Netlist to GDSII conversions at block level/SS/SoC - Execute multiple tape outs with a focus on low power implementation - Experience in floor planning, partitioning, integration at Subsystem/Chip - Hands-on exposure to lower technology nodes (3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, etc.) - Floor planning, placement optimizations, CTS, and routing - Block/top-level signoff STA, physical verification checks (DRC/LVS/ERC/antenna), and reliability checks (IR/EM/Xtalk) - Expertise in industry-standard EDA tools from Synopsys, Cadence, and Mentor - Exposure to DMSA flow for ECO generation and implementation - Good knowledge of VLSI processes and scripting in TCL, Perl Qualifications Required: - Bachelor's/Master's degree in Electrical/Electronics Engineering or equivalent - 4 to 10 years of experience in Physical Design - Proficiency in industry-standard EDA tools such as ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC, Redhawk, Voltage Storm - Skills in Physical design, PNR, and PD Flow - Strong analytical and problem-solving skills - Excellent communication and teamwork abilities About UST: UST is a global digital transformation solutions provider that has been making a real impact through transformation for over 20 years. With a workforce of over 30,000 employees in 30 countries, UST partners with leading companies worldwide, embedding innovation and agility into their clients" organizations. UST's deep domain expertise and future-proof philosophy ensure they build solutions for boundless impact, touching billions of lives in the process.,