4.0 - 10.0 years

0 Lacs

karnataka

On-site

As a Physical Design Engineer with 4 to 10 years of experience, you are expected to possess a strong foundation in the Basic Fundamentals of C-MOS technology. Your role entails a deep understanding of the PD Flow for both flat and hierarchical designs. You should be proficient in independently handling RTL/Netlist to GDSII conversions at block level, subsystem, and SoC, with a track record of multiple tape outs emphasizing low power implementations. Experience in floor planning, partitioning, and integration at the Subsystem/Chip level would be advantageous. Additionally, you should have practical experience with lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm. Key Respo...

Posted 1 week ago

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Associate III - VLSI-PNR-Aster UST Global

3.0 - 10.0 years

0 Lacs

bangalore, karnataka

On-site

Role Overview: As a Physical Design Engineer at UST, you will be expected to have a strong understanding of the Basic Fundamentals of C-MOS technology and a comprehensive knowledge of the PD Flow for flat and hierarchical designs. Your responsibilities will include independently handling RTL/Netlist to GDSII conversions at block level/SS/SoC and executing multiple tape outs with a focus on low power implementation. Experience in floor planning, partitioning, integration at Subsystem/Chip, and hands-on exposure to lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, etc., will be crucial. You will also be involved in floor planning, placement optimizations, clock tree synthes...

Posted 1 month ago

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