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3.0 - 10.0 years
0 Lacs
bangalore, karnataka
On-site
Role Overview: As a Physical Design Engineer at UST, you will be expected to have a strong understanding of the Basic Fundamentals of C-MOS technology and a comprehensive knowledge of the PD Flow for flat and hierarchical designs. Your responsibilities will include independently handling RTL/Netlist to GDSII conversions at block level/SS/SoC and executing multiple tape outs with a focus on low power implementation. Experience in floor planning, partitioning, integration at Subsystem/Chip, and hands-on exposure to lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, etc., will be crucial. You will also be involved in floor planning, placement optimizations, clock tree synthes...
Posted 4 days ago
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