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Associate III - VLSI-PNR-Aster

Associate III - VLSI-PNR-Aster

UST

4 - 10 years

0 Lacs

karnataka

Posted:1 week ago| Platform: Shine logo

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Skills Required

physical design pnr pd flow

Work Mode

On-site

Job Type

Full Time

Job Description

As a Physical Design Engineer with 4 to 10 years of experience, you are expected to possess a strong foundation in the Basic Fundamentals of C-MOS technology. Your role entails a deep understanding of the PD Flow for both flat and hierarchical designs. You should be proficient in independently handling RTL/Netlist to GDSII conversions at block level, subsystem, and SoC, with a track record of multiple tape outs emphasizing low power implementations. Experience in floor planning, partitioning, and integration at the Subsystem/Chip level would be advantageous. Additionally, you should have practical experience with lower technology nodes such as 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm. Key Responsibilities: - Execute floor planning, placement optimizations, clock tree synthesis (CTS), and routing. - Perform block/top level signoff static timing analysis (STA) and physical verification including DRC/LVS/ERC/antenna checks. - Conduct reliability checks such as IR/EM/Xtalk. - Utilize industry-standard EDA tools from Synopsys, Cadence, and Mentor like ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC, Redhawk, and Voltage Storm. - Familiarity with DMSA flow for ECO generation and implementation. - Proficiency in VLSI process and scripting using TCL, Perl. Qualifications Required: - Strong background in Physical design and PNR. - Hands-on experience with PD Flow. This job requires you to be detail-oriented, technically proficient, and adept at collaborating with cross-functional teams to deliver high-quality results in Physical Design.,

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Associate III - VLSI-PNR-Aster