ASIC Verification Lead

As an ASIC Verification Lead at Eviden, a global leader in data-driven digital transformation, you will play a key role in integrating the ASIC functional verification team. The ASICs developed by Eviden include network controllers, routers, and cache coherence controllers for high-end and high-performance servers. Your expertise will be instrumental in utilizing Constraint-Random, Coverage Driven functional verification methodologies within the UVM verification framework to ensure thorough verification of complex ASIC designs. Your main responsibilities will include acquiring in-depth knowledge of ASIC architecture and microarchitecture by studying specifications and collaborating with architecture and logical design teams. You will actively participate in defining verification strategies and methodologies, developing simulation environments, and maintaining verification specifications. Collaborating closely with the logical design team, you will write and execute test plans, develop coverage models, and verification environments using UVM-SystemVerilog/C++. Furthermore, you will be responsible for monitoring, analyzing, and debugging simulation errors, as well as assessing simulation coverage results to enhance tests and meet coverage targets efficiently. Your role will also involve providing recommendations on tools and methodologies to enhance productivity, along with mentoring junior engineers to ensure maintainable and reusable code across projects. To excel in this role, you should have a proven track record of successful verification of complex SoCs or ASICs and a strong command of UVM or equivalent verification methodologies. Proficiency in developing Constraint-Random/Coverage-Driven verification environments in SystemVerilog/C++ is essential, along with expertise in simulation tools and coverage database visualization tools. Your ability to develop effective test plans, swiftly identify functional defects, and implement solutions under tight deadlines will be crucial. The ideal candidate will have a minimum of 7 years of experience and hold a Master's or Engineer's degree in Electronics and Communication Engineering. If you are passionate about driving innovation in ASIC verification and possess strong problem-solving skills, we invite you to join our dynamic team at Eviden and contribute to shaping the future of digital transformation. Let's grow together at Eviden.,