ASIC VERIFICATION ENGINEER

THE ROLE:

We are currently looking for MTS ASIC Verification Engineers who will be involved in all aspects of AMDs next generation Data center network products. This includes verifying designs using the latest UVM standard and developing comprehensive test plans to ensure coverage closure. The position allows exposure to all aspect of ASIC design stages.

Our products are aimed at making Data Centre Networking solutions more effective. This is a highly strategic and important part of AMD s business, targeting a set of customers that includes the most successful internet and cloud companies in the world.

Successful candidate will work alongside an experienced design and architecture teams and will thus have enormous opportunities for learning and self-development. The position is likely to require some travel.

THE PERSON:

• Creative innovator and thinker who loves technical problems and detail-oriented tasks
• Exhibits relentless commitment to help the team meet quality and development goals on schedule with high quality
• Drives to learn and perform at their highest potential in a technical capacity
• Thrives in both a team environment and in individual contribution.
• Able to lead a small team of engineers working towards a common objective
• Able to learn independently and acquire new skills required for the job
• Communicates openly and clearly in meetings, presentations, emails, and reports

KEY RESPONSIBILITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Experience with PCIe and/or Ethernet protocols
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributedcomputeenvironment.
• Exposure to simulation profile, efficiency improvement, acceleration
• Good understanding and hands-on experience in the UVM concepts andSystem Veriloglanguage
• Scripting language experience: Python, Ruby,Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset
• Desirableassetswith prior exposure to network processors.

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree in computer engineering/Electrical Engineering