Posted:1 day ago|
Platform:
Work from Office
Full Time
- Expertise in ASIC physical design
- Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR.
- Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.
- Expertise in floor planning, methodology setup, and signoff processes for large IPs.
- Expertise in scripting (TCL, Python, Perl) for design flow automation.
- Drive SOC-level floor planning, partitioning, and die size estimation.
- Manage hierarchical design flows, including block-level pin placement and HFN
implementation.
- Lead clock planning strategies at SOC and subsystem levels (Mesh/Tree).
- Provide technical mentorship to junior engineers and cross-functional teams.
- Own bump planning, including GPIO placement, pad ring generation, hard IP bump
integration, and RDL routing.
- Strong communication and problem-solving abilities
- Collaborate with RTL, STA, and verification teams for design closure.
- Utilize multiple EDA tools like Synopsys Fusion Compiler, ICC2, Design Compiler
Vhunt4u
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.
We have sent an OTP to your contact. Please enter it below to verify.
Instantly access job listings, apply easily, and track applications.
Practice Python coding challenges to boost your skills
Start Practicing Python Now
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
5.0 - 10.0 Lacs P.A.
7.0 - 8.0 Lacs P.A.
