ASIC Digital Design, Sr Engineer

Job Description

Create comprehensive test plans and verification strategies aligned with specifications Develop modular and reusable testbenches using SystemVerilog Write both directed and random tests to validate functionality Perform functional and code coverage modeling, analysis, and reviews Debug mismatches between RTL design and C-model behavior Integrate internal and third-party verification IP for full-chip simulations Review and optimize existing test suites and verification environments Mentor junior engineers and assist in skill development Ensure test plans are fully traceable to design specifications using coverage databases The Impact You Will Have: Lead innovation in processor and IP verification strategies Strengthen IP quality through rigorous and structured verification practices Enhance verification efficiency through test automation and coverage closure Contribute to the success of Synopsys industry-leading silicon IP Help standardize and refine verification flows and methodologies Foster a culture of mentorship and continuous improvement within the team What You'll Need: Bachelor's degree in Engineering (preferably from a reputed institution) 36 years of experience in hardware verification Experience in microprocessor or processor-based system verification is a strong plus Proficient in SystemVerilog, Verilog, and UVM/OVM methodologies Skilled in C programming, assembly language, Perl scripting, and makefiles Familiarity with advanced verification techniques such as formal methods, low-power, and functional safety is advantageous