ASIC Design and STA Engineer

Role Overview: NVIDIA is seeking a talented ASIC STA Engineer to join the Networking Silicon engineering team. As an ASIC STA Engineer, you will play a crucial role in developing high-speed communication devices for AI platforms. This is an exciting opportunity to work on groundbreaking large-scale chips and contribute to a technology-focused company. Key Responsibilities: - Take charge of full chip and/or chiplet level STA convergence from the early stages to signoff. - Participate in top-level floor plan and clock planning. - Collaborate with CAD signoff flows and methodologies for optimization. - Integrate digital partitions and analog IPs" timing, provide feedback to PD/RTL, and drive convergence. - Define and implement constraints for various work modes in collaboration with logic design and DFT engineers, optimizing for runtime and efficiency. Qualifications Required: - B.SC./ M.SC. in Electrical Engineering/Computer Engineering. - 3-8 years of experience in physical design and STA. - Proven expertise in RTL2GDS and STA design and convergence. - Familiarity with physical design EDA tools like Synopsys, Cadence, etc. - Hands-on experience in STA from early stages to signoff using Synopsis Primetime. Deep understanding of timing concepts is essential. - Strong team player. Additional Company Details: NVIDIA is a forward-thinking organization that values creativity, autonomy, and challenges. Joining NVIDIA means being part of a diverse and supportive environment where everyone is encouraged to deliver their best work. If you are a self-motivated engineer who enjoys tackling complex problems, this is your opportunity to be part of the best physical design team in the industry. Please note the Job Reference number: JR1995153,