ASIC Design and STA Engineer

As an ASIC STA Engineer at NVIDIA, you will be an integral part of the outstanding Networking Silicon engineering team, contributing to the development of cutting-edge high-speed communication devices for AI platforms. Your role will involve the following key responsibilities: - Be responsible for full chip and/or chiplet level STA convergence from the early stages to signoff. - Participate in top-level floor plan and clock planning activities. - Collaborate with CAD signoff flows and methodologies to optimize performance. - Integrate timing for digital partitions and analog IPs, providing feedback to PD/RTL and driving convergence. - Define and implement constraints for various work modes in close collaboration with logic design and DFT engineers. The qualifications required for this role include: - B.SC./M.SC. in Electrical Engineering/Computer Engineering. - 3-8 years of experience in physical design and STA. - Proven expertise in RTL2GDS and STA design and convergence. - Familiarity with physical design EDA tools (e.g., Synopsys, Cadence). - Hands-on experience with STA from early stages to signoff using Synopsis Primetime, with a deep understanding of timing concepts. - Strong teamwork skills. At NVIDIA, we are dedicated to fostering a diverse and supportive work environment where every individual is encouraged to excel. If you are a creative and autonomous engineer who thrives on challenges, and if you are ready to unleash your full potential, join us and be a part of our innovative physical design team. Please note that the company details are not provided in the job description.,