3.0 - 8.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: NVIDIA is seeking a talented ASIC STA Engineer to join the Networking Silicon engineering team. As an ASIC STA Engineer, you will play a crucial role in developing high-speed communication devices for AI platforms. This is an exciting opportunity to work on groundbreaking large-scale chips and contribute to a technology-focused company. Key Responsibilities: - Take charge of full chip and/or chiplet level STA convergence from the early stages to signoff. - Participate in top-level floor plan and clock planning. - Collaborate with CAD signoff flows and methodologies for optimization. - Integrate digital partitions and analog IPs" timing, provide feedback to PD/RTL, and drive co...

Posted 4 days ago

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ASIC Design and STA Engineer NVIDIA

3.0 - 8.0 years

0 Lacs

hyderabad, telangana, india

On-site

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

Posted 3 weeks ago

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ASIC Design and STA Engineer NVIDIA

3.0 - 8.0 years

0 Lacs

hyderabad, telangana

On-site

As an ASIC STA Engineer at NVIDIA, you will be an integral part of the outstanding Networking Silicon engineering team, contributing to the development of cutting-edge high-speed communication devices for AI platforms. Your role will involve the following key responsibilities: - Be responsible for full chip and/or chiplet level STA convergence from the early stages to signoff. - Participate in top-level floor plan and clock planning activities. - Collaborate with CAD signoff flows and methodologies to optimize performance. - Integrate timing for digital partitions and analog IPs, providing feedback to PD/RTL and driving convergence. - Define and implement constraints for various work modes i...

Posted 2 months ago

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