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Capgemini
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Analog Layout Engineer

Analog Layout Engineer

Capgemini

4 - 9 years

5 - 9 Lacs

bengaluru

Posted:21 hours ago| Platform:

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Skills Required

debugging cloud emerging technologies layout design eda finfet design ai lvs retail eda tools

Work Mode

Work from Office

Job Type

Full Time

Job Description

About The Role
About the Job
Choosing Capgemini means choosing a place where you’ll be empowered to shape your career, supported by a collaborative global community, and inspired to reimagine what’s possible. Join us in helping leading Consumer Products and Retail Services (CPRS) organizations unlock the value of technology and drive scalable, sustainable growth Your Role

To work independently on block/IP levels analog layout design from schematic.

Estimating the Area, Optimizing Floorplan, Routing and Verifications.

Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below.

Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.

Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally.

Your Profile

Analog Layout Design (Block/IP level) - 4 to 10 Years

LVS/DRC Debugging

FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)

EDA Tools

Cadence Virtuoso Editor

Calibre RVE

Layout Optimization

Area estimation

Floorplanning

Routing

What You’ll Love About Working Here
We value flexibility and support our employees with Hybrid work options and adaptable schedules to maintain a healthy work-life balance. Our inclusive culture brings together diverse professionals committed to growth, innovation, and excellence. You’ll have access to continuous learning opportunities and certifications in emerging technologies like cloud and AI. About Us
About The Role - Grade Specific

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Analog Layout Engineer