8 - 12 years

0 Lacs

Posted:4 days ago| Platform: Shine logo

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On-site

Job Type

Full Time

Job Description

As a Senior Analog Circuit Design Engineer at BLR & HYD location with 8+ years of experience, your role will involve specializing in SerDes architecture for high-speed I/O interfaces like USB, DisplayPort, and PCIe. You will be responsible for designing and validating CDR circuits, CTLEs, Deserializer architectures, and PLLs, playing a key role in developing next-generation PHY IPs for advanced semiconductor nodes. Key Responsibilities: - Design and validate CDR circuits, CTLEs, PLLs, and Deserializer architectures. - Develop next-generation PHY IPs for advanced semiconductor nodes. - Ensure compliance with high-speed interface standards such as USB 3.x/4, DisplayPort, PCIe Gen3/Gen4/Gen5. - Utilize EDA tools like Cadence Virtuoso, Spectre, HSPICE, and layout verification tools. - Apply expertise in signal integrity, jitter analysis, and equalization techniques. Qualifications Required: - M.S. or Ph.D. in Electrical Engineering or related field. - 8+ years of experience in analog/mixed-signal IC design, specifically in SerDes PHY development. - Deep understanding of high-speed interface standards: USB 3.x/4, DisplayPort, PCIe Gen3/Gen4/Gen5. - Proficiency in EDA tools such as Cadence Virtuoso, Spectre, HSPICE, and layout verification tools. - Strong grasp of signal integrity, jitter analysis, and equalization techniques. If you are interested in this opportunity, please share your updated profile to anand.arumugam@modernchipsolutions.com or contact 9900927620.,

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