AMS Design, Verification and Layout

As an AMS Design, Verification, and Layout professional at Canvendor, you will be responsible for designing analog and mixed-signal circuits such as amplifiers, data converters, PLLs, and regulators. Your role will involve performing detailed transistor-level simulations including DC, AC, transient, PVT, and Monte Carlo analyses. Your key responsibilities will include: - Developing and maintaining behavioral models using Verilog-A/AMS and creating comprehensive testbenches for mixed-signal co-simulation with digital blocks. - Executing block-level and top-level verification, encompassing functional, corner-case, noise, and signoff simulations to ensure the design meets specifications under all conditions. - Creating physical layouts for AMS blocks, applying advanced layout techniques such as matching, shielding, and symmetry to minimize parasitic effects and performance variations. - Conducting physical verification tasks like DRC (Design Rule Check), LVS (Layout vs. Schematic), and parasitic extraction to ensure manufacturability and design integrity. - Collaborating proactively with circuit design, verification, and layout teams to deliver high-quality AMS IP on schedule and according to foundry requirements. Key Tools and Skills required for this role include proficiency in EDA Tools such as Cadence Virtuoso (schematic & layout), Spectre/HSPICE (simulation), AMS Designer/VCS AMS (co-simulation), and Calibre/Assura (physical checks). You should possess a strong knowledge of analog circuit principles, mixed-signal interaction, and layout best practices, along with good teamwork, communication, and documentation skills. If you have 4+ years of experience in Semiconductor domain, possess the necessary skills, and are looking for an immediate opportunity in Bangalore, Hyderabad, or Noida, we encourage you to share your updated CV with us at anushab@canvendor.com.,