AGM / Senior manager

Role & responsibilities

The incumbent will play a key leadership role in designing and delivering high-performance digital subsystems that form the backbone of complex defence-grade systems such as radar, electronic warfare (EW), and communication platforms. This role involves leading the architecture, development, and integration of FPGA/SoC-based digital processing pipelines, ensuring compliance with real-time, high-throughput, and mission-critical application requirements.

Preferred candidate profile

The role requires full lifecycle leadership from system architecture to hardware-software integration, verification, and deployment. The candidate will manage cross-functional coordination across signal processing, embedded systems, and hardware teams.

• Lead architecture, design, and implementation of digital subsystems including FPGAs, SoCs, high-speed interfaces (PCIe, DDR, JESD, SERDES), and DSP pipelines.

• Drive design of digital processing algorithms for radar, EW, and signal intelligence systems using VHDL/Verilog/SystemVerilog.

• Collaborate with RF, Antenna, Firmware, and Embedded teams for real-time co-design and optimization.

• Oversee design entry, synthesis, place-and-route, timing closure, and board-level bring-up across Xilinx, Intel (Altera), or Microsemi platforms.

• Ensure compliance with MIL-STD-461/810, DO-254, and other relevant certification frameworks.

• Lead validation through simulations, lab testing, and field trials using logic analyzers, protocol analyzers, and automated test benches.

• Mentor a team of digital engineers and establish best practices in version control, documentation, and verification methodologies (e.g., UVM, ModelSim, Vivado).

• Engage with DRDO labs, defence PSUs, and academic partners for advanced co-development initiatives.

• Drive innovation through IP generation, reconfigurable architectures, and digital roadmap planning.