59 Tetramax Jobs - Page 3

Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies f...

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Understand the design specification , Memory and Memory BIST engine connections Develop the verification environment and test bench and creating testcases. Debug fails using waveform, trace tools and debug RTL code Develop skills in IBM Functional verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 + years of experience in Design Verification - demon...

Role & responsibilities DFT Engineer Must-Have: •Tools: Synopsys DFT Compiler, Tessent, Mentor TestKompress, Tetramax, Fastscan •Techniques: •Scan Insertion (ATPG) •Boundary Scan (JTAG) •MBIST, LBIST •Compression techniques •Stuck-at, Transition fault models •Simulation and validation of test vectors •DFT signoff and coverage reports •STA constraint generation for test modes Nice-to-Haves: •Tapeout experience •Knowledge of low-power test techniques •Integration of DFT at SoC level Common Green Flags Across Roles: •Product or IP ownership •Clear mention of project responsibilities (not just team contribution) •Mention of tapeouts or silicon-proven designs •Stable employment history (avoiding ...

ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical desig...

Position: DFT Lead Engineer ( Cluster porject with 7-8 Junior team) Location: Bangalore, India Experience: 8+ years in ASIC/SoC DFT About the Role We are seeking an experienced Design-for-Test (DFT) Lead Engineer to drive test architecture, strategy, and execution for advanced AI-centric SoCs. This role demands deep technical expertise, leadership skills, and the ability to collaborate closely with cross-functional design teams to ensure high-quality, production-ready silicon. Key Responsibilities Define and own the DFT architecture for complex AI/ML SoCs, including scan, MBIST, LBIST, JTAG, and boundary scan strategies. Drive ATPG, fault modeling, pattern generation, and compression flow fo...

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse...

Verify different functions/Components of the Server Processor chip, Memory BIST or Reset Flow and Boot Firmware. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Create/Update the test environment and code automated test scenarios and environments. Work with development and system tests team to ensure coverage criteria is met. Create/Update formal verification rules for various functions in PCIe and PIPE specification. Develop skills in IBM Functional verification tools and apply them successfully. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5+ years of exp...

Verify different functions/Components of the Server Processor chip, Memory BIST or Reset Flow and Boot Firmware. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Create/Update the test environment and code automated test scenarios and environments. Work with development and system tests team to ensure coverage criteria is met. Create/Update formal verification rules for various functions in PCIe and PIPE specification. Develop skills in IBM Functional verification tools and apply them successfully. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of exp...

Job Description: We are hiring a Design-for-Test (DFT) Engineer to work on cutting-edge SoC and FPGA designs. The ideal candidate should have a solid background in digital design and hands-on experience with industry-standard DFT tools and fault models. Responsibilities: • Collaborate with design teams to integrate and validate DFT structures across IP and SoC levels. • Implement Scan Compression techniques and develop test strategies for stuck-at, transition, and delay faults. • Use tools such as TestKompress and Tessent for pattern generation, MBIST, and fault diagnosis. • Perform scan retargeting and assist in silicon debug for scan and MBIST failures. • Support post-silicon yield improve...